EDN

4-bit ALU using VHDL

The project is a 4-bit ALU in VHDL with a total of 16 operations which includes various arithmetic, logical and data calculations performed by coding the ALU in VHDL code. The project is a 4-bit ALU ...
Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
Electronic Design

New App From The Mathworks Generates HDL Code From System Models

[September 18, 2006] The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It ...
GamesIndustry

Bazix introduces low-cost One Chip computer with a historical touch

GRONINGEN, July 11th, 2005 - The Dutch company Bazix, in co-operation with the Japanese companies ASCII and MSX Association, has started taking pre-orders on the One Chip MSX, a new computer system ...