EDN

How to raise the RTL abstraction level and design conciseness with SystemVerilog – Part 2

The new SystemVerilog coding style is also easy to read and maintain compared to the Verilog method of modelling FSM's. Example 1. FSM Modelling with SystemVerilog. SystemVerilog also provides an ...
Design-Reuse

Randsequence: SystemVerilog's unsung hero

Constrained random verification, for quite some time now, has been the default verification methodology for complex ASIC/SoC designs. Central to this methodology is the process of letting the ...
Semiconductor Engineering

Simplifying SystemVerilog Functional Coverage

Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is ...
EDN

System Verilog configurable coverage model in an OVM setup – concept of reusability

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...