EDN

Debugging and analysis with SystemVerilog test bench

The verification component of SystemVerilog has dominated the rapid adoption of the language. The new verification syntax in the language allows for dramatic productivity gains in the verification ...
Semiconductor Engineering

Debug This! How To Simplify Coverage Analysis And Closure

For years the process of ASIC and FPGA design and verification debug consisted primarily of comprehending the structure and source code of the design with waveforms showing activity over time, based ...
Design-Reuse

SpringSoft Introduces Structured Method for SystemVerilog Testbench Debug and Analysis

Hsinchu, Taiwan, May 18, 2009 - SpringSoft, Inc. (TAIEX: 2473), a global supplier of specialized IC design software, today announced comprehensive SystemVerilog Testbench (SVTB) debug support with the ...
EDN

NPTest debuts failure analysis and debug tool

SAN JOSE–NPTest Inc., formerly known as Schlumberger Semiconductor Solutions, here today introduced an IC failure analysis and debug tool that measures and validates flip-chip devices and other ...
Business Wire

SpringSoft, Vennsa Technologies Join Forces to Increase Verification Productivity with Interoperable Chip Debug and Analysis Solutions

As an integrated ecosystem, the Verdi and OnPoint products offer design and verification engineers a unified push-button flow for functional debugging, root cause analysis and design navigation. The ...